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I wrote a detailed description of R800 for the Wikipedia, most of this information I gathered while making some projects using VHDL and FPGA. I hope you enjoy the info.

Very interesting. One remark, though: You write on several instances ULA (undedicated logic array) when you mean (or don't you?) ALU (arithmetic logic unit).

ULA, as in "Unidade de Lógica Aritmética"?

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ULA, as in "Unidade de Lógica Aritmética"?

Oh my mistake. I still think in portuguese most of the time, sometimes it slip through. I'm going to fix it.

Don't forget to change CISC into RISC

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Don't forget to change CISC into RISC

Wikipedia is supposed to have impartial, objective information. If we can't agree if R800 is CISC or RISC, then the information is best left out.

*CISC CISC CISC!*

*strikes the flag*

Seriously, you people should do some investigation on the subject, in stead of picking a side and acting like a teenager.
If you do the research, there's only one conclusion possible. R800 is RISC, it's the design, the name and the fact that it was always presented as a RISC CPU.

Really, the R800 opcodes are far less complex than those of an ARM CPU (ARM means Advanced RISC Machine).
R800 has very few instructions, and a relatively large register set. Most of the instructions imply a load-store architecture. You can say "Block move commands aren't very RISCy", yet the ARM has them too, just like flags.

I haven't heared any argument that the R800 would not be RISC, other than that it's based on the Z80 architecture, which is a non-argument because of what I wrote above also applies to the Z80, except that its implementation shows very few RISC characteristics (except that it's NOT microcoded, just like most RISC chips).

Compare a Z80 to a 68000 and 80386, and you will know how COMPLEX CISC really is! Compare a Z80 to an ARM, H8/300 and Atmel AVR, and you will know that the Z80 architecture lends itself almost perfectly for a RISC implementation.

This message is my final say on this... If you do the research I'm telling about, and you still come to the conclusion the R800 is 'CISC' then there's no hope for you... seriously. :\

6502 has very few instructions, shell we proclame Atari VCS the first RISC-architecture supercomputer?

Are you just that dumb, or are you trying to be funny?

Notice the hidden '',

R800 is a CISC CPU. There is no hope for me

GuyveR800: I know why you think the R800 is a RISC CPU, I have no problem with that, I just think you're wrong here; now is your chance to respect a different opinion.

The fact the R800 has an accumulator should be enough to not call it RISC.
I am willing to discuss things more seriously and in more depth, but that seems to be impossible

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Are you just that dumb, or are you trying to be funny?

I'm just trying to be funny, but 6205 is a lot more RISC than Z80.

And I am not trying to lure people into fights or something. I just think R800 is CISC. Feel free to not react. No need for insults and such. Thanks. Having said that:

Sonic_aka_T: R800 is CISC!!! You know that

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I am willing to discuss things more seriously and in more depth, but that seems to be impossible

Funny how you say you are willing to discuss this, but can't come up with any arguments. Well, the accumulator one... but that's it... and it's not even a good one, because it's implied by the instruction set. It has no bearing on the actual design of the CPU.
Besides, IIRC at least one major RISC CPU had an accumulator.

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Quote: Are you just that dumb, or are you trying to be funny? I'm just trying to be funny, but 6205 is a lot more RISC than Z80.

6502 has many different addressing modes, some of which incredibly complex.
It has no sign of a load-store architecture, as most instructions are of the read-modify-write kind.
Its register set is too small to be taken seriously, just 3 registers...

Everything about it shouts CISC!

You really should do more research, otherwise even more people will start thinking you're seriously lacking in the intelligence department...

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Quote: Quote: Are you just that dumb, or are you trying to be funny? I'm just trying to be funny, but 6205 is a lot more RISC than Z80. 6502 has many different addressing modes, some of which incredibly complex.

Consider this: The 6502 was produced to favour memory over internal registers, since this cuts costs and since memory was very fast back in the seventies (compared to the processor, that is). You could regard the zero page as a big register set. Now, addressing is much clearer, isn't it?

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Its register set is too small to be taken seriously, just 3 registers...

The Z80 doesn't compare favourably here, since all its registers are special-purpose. The register layout of the Z80 is, no matter the amount of registers, far less RISC-like than the 6502, which has an accumulator and two index registers and nothing else. No LDIRs here.

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Everything about it shouts CISC!

The uniform opcode size is a RISCy trait. Some would say that the instruction set is "reduced", too.

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Consider this: The 6502 was produced to favour memory over internal registers, since this cuts costs and since memory was very fast back in the seventies (compared to the processor, that is). You could regard the zero page as a big register set. Now, addressing is much clearer, isn't it?

I know this, but they are not registers, they are RAM... So a RISC implementation would be impossible, unless you put the Zero page internal to the CPU and call it registers :/

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The Z80 doesn't compare favourably here, since all its registers are special-purpose.

The 6502 registers are very limited in their use, and each have their own specialities. IMO the Z80 is much more orthogonal in this.

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The register layout of the Z80 is, no matter the amount of registers, far less RISC-like than the 6502, which has an accumulator and two index registers and nothing else. No LDIRs here.

ARM has LDIR...

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The uniform opcode size is a RISCy trait. Some would say that the instruction set is "reduced", too.

There's no uniform opcode size on 6502, neither is the instruction set 'reduced'. In fact, it's really big compared to the Z80!

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ARM has LDIR...

I'm curious - which ARM version is this and which command are you referring to? LDM/STM on an ARM is hardly the same as LDIR on Z80. As far as I know ARM does not have memory->memory copy/move commands at all.