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Hardware - R800 information

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R800 information

tfh
msx addict
Berichten: 495
Geplaatst: 01 Oktober 2004, 15:52   
snout

msx legend
Berichten: 4991
Geplaatst: 01 Oktober 2004, 15:53   
Please guyz, do you really need to try and find out how far you can go on the MRC all the time? Do you really need to keep trying to lure people into certain reactions time and time again? Do you really need to take and make things personal all the time?

The MRC is a unique discussion platform about MSX and if we were all just a bit more open towards different opinions (which, once again are inevitable in a community as big as the MSX community), perhaps a larger part of the more than 2300 members of the MRC will start and continue joining the discussions over here. Now, a small group of people are not exactly helping in creating an atmosphere in which it's nice for newbies to join in. Please, stop that. Thank you.

Back to the R800 discussion.

Some people think R800 is CISC, some think R800 is RISC. If you can't post a well-founded reply with proof why R800 would be either RISC or CISC, then just don't reply.

I suggest we refrain from cat and mouse, chicken or egg and yes it is, no it isn't - posts from now on. I expect any further posts in this topic to contain information on the R800 processor. Nothing more, nothing less.
sjoerd
msx addict
Berichten: 450
Geplaatst: 01 Oktober 2004, 16:04   
Quote:

Here you are : z80.info/zip/r800.zip

Thanks.
mars2000you
msx master
Berichten: 1723
Geplaatst: 01 Oktober 2004, 19:02   
Just a little stone in the general discussion :

http://www.giga.it.okayama-u.ac.jp/~saito/test/bbs/doc/tech30.html

On this very technical page , i can read this :

※Z80ではリフレッシュが定期的MSX-ENGINE(T9769)が行うCBRリフレッシュであり、かつCPUがCISCなのでス
テート計算でタイミングが分かるが、R800はRISCライクなので命令実行時間を計算するのが困難。よって、

Excite (bad) translation :

Since refreshment is periodical (CBR refreshment which MSX-ENGINE (T9769) performs) in Z80 and CPU is CISC, it is SU.
Although timing is known by the Tait calculation, since R800 is RISC-like, it is difficult to calculate command execution time. It depends.


[D-Tail]

msx guru
Berichten: 3019
Geplaatst: 01 Oktober 2004, 19:09   
Another (bad) translation from Babel Fish:

Quote:


* With Z80 the refreshment fixed period MSX-ENGINE (T9769) is the CBR refreshment which is done, it meaning that at the same time CPU is CISC, timing understands in the ス テート calculation, but as for R800 being to be RISC like, it is difficult to calculate instruction execution time. Depending,


dhau
msx master
Berichten: 1057
Geplaatst: 01 Oktober 2004, 21:18   
So it's RISC-like CISC-ish CPU then
Sonic_aka_T

msx guru
Berichten: 2269
Geplaatst: 01 Oktober 2004, 23:40   
yup...
GuyveR800
msx guru
Berichten: 3048
Geplaatst: 01 Oktober 2004, 23:44   
which I've been saying all along :\
sjoerd
msx addict
Berichten: 450
Geplaatst: 02 Oktober 2004, 00:33   
What about: R800 is a CISC CPU with a RISC-like implementation?
[D-Tail]

msx guru
Berichten: 3019
Geplaatst: 02 Oktober 2004, 02:49   
Are we searching for a compromise? No way!!
GuyveR800
msx guru
Berichten: 3048
Geplaatst: 02 Oktober 2004, 04:31   
RISC, RISC-like, it's all the same

As I said before, there is no such thing as a set of rules which something NEEDS to conform to in order to be called RISC... It's a design PHILOSOPHY, not a SCIENCE. ^^;
ro
msx guru
Berichten: 2346
Geplaatst: 02 Oktober 2004, 12:47   
so it's more a CRISC thingy as in "whoh, check out how CRISCY this new pretzel is!"
Sonic_aka_T

msx guru
Berichten: 2269
Geplaatst: 02 Oktober 2004, 16:02   
I much prefer CRISCY pringles...
Sonic_aka_T

msx guru
Berichten: 2269
Geplaatst: 02 Oktober 2004, 16:06   
Quote:

What about: R800 is a CISC CPU with a RISC-like implementation?

Actually, I think you're implementing a non-RISC CPU by means of RISC architecture. The CPU is RISC-like, what you're implementing has ofcourse many non-RISC traits since you're being (opcode) compatible with a non-RISC CPU.
sjoerd
msx addict
Berichten: 450
Geplaatst: 03 Oktober 2004, 20:54   
Quote:

Actually, I think you're implementing a non-RISC CPU by means of RISC architecture. The CPU is RISC-like, what you're implementing has ofcourse many non-RISC traits since you're being (opcode) compatible with a non-RISC CPU.

LOL
 
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