Schrijver
| VDP commands and screen 4
| ARTRAG
msx master
Berichten: 1685 |  Geplaatst: 30 Oktober 2005, 18:34 | This is a scroll demo without TPSET animations
Use currsors and esc to exit
The next will be with objects animated using TPSET
PS compile with sjasm
db $fe
dw startProgram,endProgram,startProgram
org $C000
; VDP ports
;
vdpport0 equ 098h ; VRAM read/write
vdpport1 equ 099h ; VDP registers read/write
vdpport2 equ 09ah ; Palette registers write
vdpport3 equ 09bh ; Indirect register write
; vdp: send value in A to VDP register
; syntax:vdp reg#
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
; (6 bytes/31 cycles)
;
MACRO vdp reg
out (vdpport1),a
ld a,reg or 010000000b
out (vdpport1),a
endm
; vdpw: send value to VDP register
; syntax:vdp reg#, value#
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
;
MACRO vdpw reg,value
ld a,value
vdp reg
endm
; scr5: set screen 5
; syntax:scr5
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
;
;
MACRO scr5
vdpw 0,6
vdpw 1,98
vdpw 8,10
endm
; scr4: set screen 4,2
; syntax:scr4
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
;
;
MACRO scr4
vdpw 0 ,4
vdpw 1 ,98
vdpw 3 ,255
vdpw 4 ,3
vdpw 5 ,63
vdpw 6 ,7
vdpw 8 ,8
vdpw 9 ,2
vdpw 10 ,0
vdpw 11 ,0
endm
MACRO page1
vdpw 2 ,6
endm
MACRO page2
vdpw 2 ,22
endm
MACRO wait_CE
.loop in a,(vdpport1) ;loop if vdp not ready (CE)
rrca
jp c,.loop
endm
MACRO pause sec
ld de,sec*60
.loop halt
dec de ; 1/6
ld a,d ; 1/4
or e ; 1/4
jp nz,.loop ; 3/10
endm
; ram2vram17: copy RAM block to VRAM (full 128Kb)
; syntax:r2v16e <RAM addr>, <VRAM addr>, <number of bytes>
; modifies: AF,HL,DE,C
; note: **** INTERRUPTS MUST BE DISABLED ****
;
MACRO ram2vram17 ram,vram,num
ld a,vram >>>16
ld hl,vram & #FFFF ; 3/10 15/158
call SetVdp_Write
ld de,num ; 3/10
ld hl,ram ; 3/10
ld c,vdpport0 ; 2/7
.loop outi ; 2/16
dec de ; 1/6
ld a,d ; 1/4
or e ; 1/4
jp nz,.loop ; 3/10
endm
; fillvram17: fill VRAM (full 128Kb)
; syntax:r2v16e <VRAM addr>, <number of bytes>, >value>
; modifies: AF,HL,DE,C
; note: **** INTERRUPTS MUST BE DISABLED ****
;
MACRO fillvram17 vram,num,value
ld a,vram >>>16
ld hl,vram & #FFFF ; 3/10 15/158
call SetVdp_Write ; 3/(17+104)
ld de,num ; 3/10
ld c,vdpport0 ; 2/7
.loop ld a,value
out (c),a
dec de ; 1/6
ld a,d ; 1/4
or e ; 1/4
jp nz,.loop ; 3/10
endm
startProgram:
ld a,8
call #5f
ld a,1
call #5f
vdpw 7,1
scr4
page1
ram2vram17 (#F920),0,256*8
ram2vram17 (#F920),256*8,256*8
ram2vram17 (#F920),256*8*2,256*8
fillvram17 128*256 ,4*128,'A'
fillvram17 128*256+ 4*128,4*128,'B'
fillvram17 128*256+ 8*128,4*128,'C'
ld bc,256*96
1 ld a,c
neg
out (vdpport0),a
dec bc
ld a,c
or b
jr nz,1B
xor a
ld hl,#1800
call SetVdp_Write
ld bc,256*3
1 ld a,c
neg
out (vdpport0),a
dec bc
ld a,c
or b
jr nz,1B
fillvram17 22*1024,256*3,'a'
.loop
halt
di
scr5
vdpw 15,2
ld de,linepage1
ld ix,(X)
call plotscreen
scr4
page2
vdpw 15,0
ei
call testdir
halt
di
scr5
vdpw 15,2
ld de,linepage2
ld ix,(X)
call plotscreen
scr4
page1
vdpw 15,0
ei
call testdir
call testesc
jp nz,.loop
xor a
call #5f
ret
testdir
CALL INDIR
LD (JOY),A
BIT 3,A
CALL Z,SPDS
LD A,(JOY)
BIT 2,A
CALL Z,SPSN
LD A,(JOY)
BIT 1,A
CALL Z,SPDW
LD A,(JOY)
BIT 0,A
CALL Z,SPUP
RET
SPDS ld a,(Y)
inc a
ld (Y),a
ret
SPSN ld a,(Y)
dec a
ld (Y),a
ret
SPDW ld a,(X)
inc a
ld (X),a
ret
SPUP ld a,(X)
dec a
ld (X),a
ret
;************************************************************
; Test if esc key is pressed.
; If pressed, z flag is positioned to 0
;************************************************************
testesc:
in a,(#aa)
and %11110000
add a,7
out (#aa),a
in a,(#a9)
and 4
ret
;*********************************************************
; ROUTIN2 (GESTIONE SPRITES)
INDIR LD A,(KEYSTK)
AND A
JP Z,KEY
STICK LD A,#0F
OUT (#A0),A
LD A,#8F
OUT (#A1),A
LD A,#0E
OUT (#A0),A
IN A,(#A2)
RET
KEY LD C,255
LD A,8
OUT (#AA),A
IN A,(#A9)
RI BIT 7,A
JP NZ,LE
RES 3,C
JP UP
LE BIT 4,A
JP NZ,UP
RES 2,C
UP BIT 5,A
JP NZ,DW
RES 0,C
DW bit 6,a
jp nz,FIRE
res 1,c
FIRE BIT 0,A
JP NZ,FIN
RES 4,C
FIN LD A,C
RET
;--------------------
STRUCT line
Xorg db 0
db 0
Yorg db 0
db 1
Xdst db 0
db 0
Ydst db 48
db 0
XN db 64
db 0
YN db 1
db 0
db 0
db 0
db #D0
ENDS
KEYSTK db 0
JOY db 0
X: db 0
Y: db 0
linepage1
line 0, 0, 0, 1, 0, 0, 48, 0
line 0, 0, 1, 1, 64, 0, 48, 0
line 0, 0, 2, 1,128, 0, 48, 0
line 0, 0, 3, 1,192, 0, 48, 0
line 0, 0, 4, 1, 0, 0, 49, 0
line 0, 0, 5, 1, 64, 0, 49, 0
line 0, 0, 6, 1,128, 0, 49, 0
line 0, 0, 7, 1,192, 0, 49, 0
line 0, 0, 8, 1, 0, 0, 50, 0
line 0, 0, 9, 1, 64, 0, 50, 0
line 0, 0,10, 1,128, 0, 50, 0
line 0, 0,11, 1,192, 0, 50, 0
line 0, 0,12, 1, 0, 0, 51, 0
line 0, 0,13, 1, 64, 0, 51, 0
line 0, 0,14, 1,128, 0, 51, 0
line 0, 0,15, 1,192, 0, 51, 0
line 0, 0,16, 1, 0, 0, 52, 0
line 0, 0,17, 1, 64, 0, 52, 0
line 0, 0,18, 1,128, 0, 52, 0
line 0, 0,19, 1,192, 0, 52, 0
line 0, 0,20, 1, 0, 0, 53, 0
line 0, 0,21, 1, 64, 0, 53, 0
linepage2
line 0, 0, 0, 1, 0, 0, 48+128, 0
line 0, 0, 1, 1, 64, 0, 48+128, 0
line 0, 0, 2, 1,128, 0, 48+128, 0
line 0, 0, 3, 1,192, 0, 48+128, 0
line 0, 0, 4, 1, 0, 0, 49+128, 0
line 0, 0, 5, 1, 64, 0, 49+128, 0
line 0, 0, 6, 1,128, 0, 49+128, 0
line 0, 0, 7, 1,192, 0, 49+128, 0
line 0, 0, 8, 1, 0, 0, 50+128, 0
line 0, 0, 9, 1, 64, 0, 50+128, 0
line 0, 0,10, 1,128, 0, 50+128, 0
line 0, 0,11, 1,192, 0, 50+128, 0
line 0, 0,12, 1, 0, 0, 51+128, 0
line 0, 0,13, 1, 64, 0, 51+128, 0
line 0, 0,14, 1,128, 0, 51+128, 0
line 0, 0,15, 1,192, 0, 51+128, 0
line 0, 0,16, 1, 0, 0, 52+128, 0
line 0, 0,17, 1, 64, 0, 52+128, 0
line 0, 0,18, 1,128, 0, 52+128, 0
line 0, 0,19, 1,192, 0, 52+128, 0
line 0, 0,20, 1, 0, 0, 53+128, 0
line 0, 0,21, 1, 64, 0, 53+128, 0
;--------------------
plotscreen:
ld c,vdpport3
rept 22
ld hl,de
vdpw 17,32
ld a,ixh
add a,(hl)
out (c),a
inc hl
outi
ld a,ixl
add a,(hl)
out (c),a
inc hl
outi
dw #A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED
ld hl,15
add hl,de
ex de,hl
wait_CE
endm
ret
;
;Set VDP port #98 to start writing at address AHL (17-bit)
;
SetVdp_Write: rlc h
rla
rlc h
rla
srl h
srl h
vdp 14 ;set bits 15-17
ld a,l ;set bits 0-7
out (vdpport1),a
ld a,h ;set bits 8-14
or 64 ; + write access
out (vdpport1),a
ret
;
;Set VDP port #98 to start reading at address AHL (17-bit)
;
SetVdp_Read: rlc h
rla
rlc h
rla
srl h
srl h
vdp 14 ;set bits 15-17
ld a,l ;set bits 0-7
out (vdpport1),a
ld a,h ;set bits 8-14
; + read access
out (vdpport1),a
ret
;
;In: HL = pointer to 15-byte VDP command data
;Out: HL = updated
;
DoCopy:
vdpw 17,32
ld c,vdpport3
rept 15
outi
endm
ret
; comandi VDP traccia blocco PIENO veloce (HMMV)
testdat1Y
db 0,0 ; origine X
db 48,0 ; origine Y
db 64,0 ; destinazione X
db 48+128,0 ; destinazione Y
db 192,0 ; dimensione X blocchi
db 6,0 ; dimensione Y blocchi
db #00,#00,#D0
testdat2Y
db 192,0 ; origine X
db 48,0 ; origine Y
db 0,0 ; destinazione X
db 49+128,0 ; destinazione Y
db 64,0 ; dimensione X blocchi
db 5,0 ; dimensione Y blocchi
db #00,#00,#D0
testdat11Y
db 0,0 ; origine X
db 48+128,0 ; origine Y
db 64,0 ; destinazione X
db 48,0 ; destinazione Y
db 192,0 ; dimensione X blocchi
db 6,0 ; dimensione Y blocchi
db #00,#00,#D0
testdat22Y
db 192,0 ; origine X
db 48+128,0 ; origine Y
db 0,0 ; destinazione X
db 49,0 ; destinazione Y
db 64,0 ; dimensione X blocchi
db 5,0 ; dimensione Y blocchi
db #00,#00,#D0
testdat1X
db 0,0 ; origine X
db 48,0 ; origine Y
db 2,0 ; destinazione X
db 48+128,0 ; destinazione Y
db 254,0 ; dimensione X blocchi
db 6,0 ; dimensione Y blocchi
db #00,#00,#D0
testdat2X
db 62,0 ; origine X
db 48,0 ; origine Y
db 0,0 ; destinazione X
db 48+128,0 ; destinazione Y
db 2,0 ; dimensione X blocchi
db 6,0 ; dimensione Y blocchi
db 'A',#00,12 ;#D0
testdat11X
db 0,0 ; origine X
db 48+128,0 ; origine Y
db 2,0 ; destinazione X
db 48,0 ; destinazione Y
db 254,0 ; dimensione X blocchi
db 6,0 ; dimensione Y blocchi
db #00,#00,#D0
testdat22X
db 62,0 ; origine X
db 48+128,0 ; origine Y
db 0,0 ; destinazione X
db 48,0 ; destinazione Y
db 2,0 ; dimensione X blocchi
db 6,0 ; dimensione Y blocchi
db 'A',#00,12 ;#D0
cycleX:
ld bc,62*256+0
call .util
ret
ld bc,126*256+64
call .util
ld bc,190*256+128
call .util
ld bc,254*256+192
.util
ld (ix+0),b
ld (ix+4),c
ld hl,ix
1 in a,(vdpport1) ;loop if vdp not ready (CE)
rrca
jp c,1B
call DoCopy
ret
endProgram:
END
| | manuel
msx guru
Berichten: 3447 | Geplaatst: 30 Oktober 2005, 21:56 | Quote:
| @ manuel
I am considering to do something like the one you propose, but first a question
Do you see the whole idea from my text ?
|
I get the rough idea, but I'm not a hardcore VDP/ASM programmer at all...
Btw, when copy-pasting the above text into an editor, and running sjasm on it, I get loads of errors. How about putting a binary somewhere, so that everyone can see the effect? | | ARTRAG
msx master
Berichten: 1685 | Geplaatst: 31 Oktober 2005, 00:23 | Strange that you get errors
btw I do not have an URL,
send me an email and I will send you the binary
| | ARTRAG
msx master
Berichten: 1685 | Geplaatst: 31 Oktober 2005, 01:13 | Manuel, here follows a shortned version of the same program and its
compiled version from sjasm.
As you can see the compilation is OK, youst copy the text in an ascii file ("test2.asm"  and run
sjasm tes2.asm
then in basic do
bload"test2.out",r
should you find problems send me and email
db $fe
dw startProgram,endProgram,startProgram
org $C000
; VDP ports
;
vdpport0 equ 098h ; VRAM read/write
vdpport1 equ 099h ; VDP registers read/write
vdpport2 equ 09ah ; Palette registers write
vdpport3 equ 09bh ; Indirect register write
; vdp: send value in A to VDP register
; syntax:vdp reg#
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
; (6 bytes/31 cycles)
;
MACRO vdp reg
out (vdpport1),a
ld a,reg or 010000000b
out (vdpport1),a
endm
; vdpw: send value to VDP register
; syntax:vdp reg#, value#
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
;
MACRO vdpw reg,value
ld a,value
vdp reg
endm
; scr5: set screen 5
; syntax:scr5
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
;
;
MACRO scr5
vdpw 0,6
vdpw 1,98
vdpw 8,10
endm
; scr4_int: set screen 4,2
; syntax:scr4
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
;
;
MACRO scr4_init
vdpw 0 ,4
vdpw 1 ,98
vdpw 3 ,255
vdpw 4 ,3
vdpw 5 ,63
vdpw 6 ,7
vdpw 8 ,8
vdpw 9 ,2
vdpw 10 ,0
vdpw 11 ,0
endm
MACRO scr4
vdpw 0 ,4
vdpw 1 ,98
vdpw 8 ,8
endm
MACRO page1
vdpw 2 ,6
endm
MACRO page2
vdpw 2 ,22
endm
MACRO wait_CE
.loop in a,(vdpport1) ;loop if vdp not ready (CE)
rrca
jp c,.loop
endm
MACRO pause sec
ld de,sec*60
.loop halt
dec de ; 1/6
ld a,d ; 1/4
or e ; 1/4
jp nz,.loop ; 3/10
endm
; ram2vram17: copy RAM block to VRAM (full 128Kb)
; syntax:r2v16e <RAM addr>, <VRAM addr>, <number of bytes>
; modifies: AF,HL,DE,C
; note: **** INTERRUPTS MUST BE DISABLED ****
;
MACRO ram2vram17 ram,vram,num
ld a,vram >>>16
ld hl,vram & #FFFF ; 3/10 15/158
call SetVdp_Write
ld de,num ; 3/10
ld hl,ram ; 3/10
ld c,vdpport0 ; 2/7
.loop outi ; 2/16
dec de ; 1/6
ld a,d ; 1/4
or e ; 1/4
jp nz,.loop ; 3/10
endm
; fillvram17: fill VRAM (full 128Kb)
; syntax:r2v16e <VRAM addr>, <number of bytes>, >value>
; modifies: AF,HL,DE,C
; note: **** INTERRUPTS MUST BE DISABLED ****
;
MACRO fillvram17 vram,num,value
ld a,vram >>>16
ld hl,vram & #FFFF ; 3/10 15/158
call SetVdp_Write ; 3/(17+104)
ld de,num ; 3/10
ld c,vdpport0 ; 2/7
.loop ld a,value
out (c),a
dec de ; 1/6
ld a,d ; 1/4
or e ; 1/4
jp nz,.loop ; 3/10
endm
startProgram:
ld a,1
call #5f
vdpw 7,1
scr4_init
page1
ram2vram17 (#F920),0,256*8
ram2vram17 (#F920),256*8,256*8
ram2vram17 (#F920),256*8*2,256*8
fillvram17 #2000,256*8*3,#31
fillvram17 128*256,96*128,r
fillvram17 #1800,256*3,' '
fillvram17 #5800,256*3,' '
.loop
halt
scr5
vdpw 15,2
ld de,linepage1
ld ix,(X)
call plotscreen
scr4
page2
vdpw 15,0
call testdir
halt
scr5
vdpw 15,2
ld de,linepage2
ld ix,(X)
call plotscreen
scr4
page1
vdpw 15,0
call testdir
call testesc
jp nz,.loop
xor a
call #5f
ret
;************************************************************
; Test if esc key is pressed.
; If pressed, z flag is positioned to 0
;************************************************************
testesc:
in a,(#aa)
and %11110000
add a,7
out (#aa),a
in a,(#a9)
and 4
ret
;*********************************************************
; I/O
;*********************************************************
testdir
ld a,8
out (#aa),a
in a,(#a9)
ld hl,X
.ri bit 7,a
jp nz,.le
inc (hl)
jp .up
.le bit 4,a
jp nz,.up
dec (hl)
.up ld hl,Y
bit 5,a
jp nz,.dw
dec (hl)
.dw bit 6,a
jp nz,.fire
inc (hl)
.fire ;bit 0,a
ret
;--------------------
STRUCT line
Xorg db 0
db 0
Yorg db 0
db 1
Xdst db 0
db 0
Ydst db 48
db 0
XN db 64
db 0
YN db 1
db 0
db 0
db 0
db #D0
ENDS
X: db 0
Y: db 0
linepage1
line 0, 0, 0, 1, 0, 0, 48, 0
line 0, 0, 1, 1, 64, 0, 48, 0
line 0, 0, 2, 1,128, 0, 48, 0
line 0, 0, 3, 1,192, 0, 48, 0
line 0, 0, 4, 1, 0, 0, 49, 0
line 0, 0, 5, 1, 64, 0, 49, 0
line 0, 0, 6, 1,128, 0, 49, 0
line 0, 0, 7, 1,192, 0, 49, 0
line 0, 0, 8, 1, 0, 0, 50, 0
line 0, 0, 9, 1, 64, 0, 50, 0
line 0, 0,10, 1,128, 0, 50, 0
line 0, 0,11, 1,192, 0, 50, 0
line 0, 0,12, 1, 0, 0, 51, 0
line 0, 0,13, 1, 64, 0, 51, 0
line 0, 0,14, 1,128, 0, 51, 0
line 0, 0,15, 1,192, 0, 51, 0
line 0, 0,16, 1, 0, 0, 52, 0
line 0, 0,17, 1, 64, 0, 52, 0
line 0, 0,18, 1,128, 0, 52, 0
line 0, 0,19, 1,192, 0, 52, 0
line 0, 0,20, 1, 0, 0, 53, 0
line 0, 0,21, 1, 64, 0, 53, 0
linepage2
line 0, 0, 0, 1, 0, 0, 48+128, 0
line 0, 0, 1, 1, 64, 0, 48+128, 0
line 0, 0, 2, 1,128, 0, 48+128, 0
line 0, 0, 3, 1,192, 0, 48+128, 0
line 0, 0, 4, 1, 0, 0, 49+128, 0
line 0, 0, 5, 1, 64, 0, 49+128, 0
line 0, 0, 6, 1,128, 0, 49+128, 0
line 0, 0, 7, 1,192, 0, 49+128, 0
line 0, 0, 8, 1, 0, 0, 50+128, 0
line 0, 0, 9, 1, 64, 0, 50+128, 0
line 0, 0,10, 1,128, 0, 50+128, 0
line 0, 0,11, 1,192, 0, 50+128, 0
line 0, 0,12, 1, 0, 0, 51+128, 0
line 0, 0,13, 1, 64, 0, 51+128, 0
line 0, 0,14, 1,128, 0, 51+128, 0
line 0, 0,15, 1,192, 0, 51+128, 0
line 0, 0,16, 1, 0, 0, 52+128, 0
line 0, 0,17, 1, 64, 0, 52+128, 0
line 0, 0,18, 1,128, 0, 52+128, 0
line 0, 0,19, 1,192, 0, 52+128, 0
line 0, 0,20, 1, 0, 0, 53+128, 0
line 0, 0,21, 1, 64, 0, 53+128, 0
;--------------------
plotscreen:
ld c,vdpport3
rept 22
ld hl,de
vdpw 17,32
ld a,ixl
add a,(hl)
out (vdpport3),a
inc hl
outi
ld a,ixh
add a,(hl)
out (vdpport3),a
inc hl
outi
dw #A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED
ld hl,15
add hl,de
ex de,hl
wait_CE
endm
ret
;
;Set VDP port #98 to start writing at address AHL (17-bit)
;
SetVdp_Write: rlc h
rla
rlc h
rla
srl h
srl h
vdp 14 ;set bits 15-17
ld a,l ;set bits 0-7
out (vdpport1),a
ld a,h ;set bits 8-14
or 64 ; + write access
out (vdpport1),a
ret
endProgram:
END
| | ARTRAG
msx master
Berichten: 1685 | Geplaatst: 02 November 2005, 12:19 | This improved version uses only 4 copies !!! this improvement
comes by a Magoo's idea, only the horozontal scroll works for now,
but I am on a new version that has vertical scroll too at the cost of 5 copies...!!!
The amazing things are that this is 100% VDP work and the screen update
is done at every frame and and can scroll at any speed,
i.e. no incremental scrolls like in the first versions!!!
Enjoy
db $fe
dw startProgram,endProgram,startProgram
org $B000
; VDP ports
;
vdpport0 equ 098h ; VRAM read/write
vdpport1 equ 099h ; VDP registers read/write
vdpport2 equ 09ah ; Palette registers write
vdpport3 equ 09bh ; Indirect register write
; vdp: send value in A to VDP register
; syntax:vdp reg#
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
; (6 bytes/31 cycles)
;
MACRO vdp reg
out (vdpport1),a
ld a,reg or 010000000b
out (vdpport1),a
endm
; vdpw: send value to VDP register
; syntax:vdp reg#, value#
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
;
MACRO vdpw reg,value
ld a,value
vdp reg
endm
MACRO set_vdp_wrt vram
vdpw 14,vram >>>13 ;set bits 16-14
ld a,vram & #FF ;set bits 0-7
out (vdpport1),a
ld a,((vram >>>7) & 0011111111b) or 64 ;set bits 8-14 + write access
out (vdpport1),a
endm
; scr4_int: set screen 4,2
; syntax:scr4
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
;
;
MACRO scr4_init
vdpw 0 ,4
vdpw 1 ,98
vdpw 3 ,255
vdpw 4 ,3
vdpw 5 ,63
vdpw 6 ,7
vdpw 8 ,8
vdpw 9 ,2
vdpw 10 ,0
vdpw 11 ,0
endm
MACRO scr5
vdpw 0,6
vdpw 1,34
vdpw 8,10
endm
MACRO scr4
vdpw 0 ,4
vdpw 1 ,98
vdpw 8 ,8
endm
MACRO page1
vdpw 2 ,6
endm
MACRO page2
vdpw 2 ,22
endm
; note: **** SET S#2 BEFORE CALLING !!! ****
MACRO wait_CE
.loop in a,(vdpport1) ;loop if vdp not ready (CE)
rrca
jp c,.loop
endm
; note: **** SET S#1 BEFORE CALLING !!! ****
MACRO wait_FH
.wvint
in a,(vdpport1)
rrca
jp nc,.wvint
endm
; wait_hbl: Wait for a complete line
; syntax:wait_hbl
; modifies: A
; note: **** INTERRUPTS MUST BE DISABLED ****
; note: **** SET S#2 BEFORE CALLING !!! ****
;
MACRO wait_hbl
.VA_YM
in a,(vdpport1)
and %00100000
jp nz,.VA_YM
.VB_YM
in a,(vdpport1)
and %00100000
jp z,.VB_YM
endm
MACRO pause sec
ld de,sec*60
.loop halt
dec de ; 1/6
ld a,d ; 1/4
or e ; 1/4
jp nz,.loop ; 3/10
endm
; ram2vram17: copy RAM block to VRAM (full 128Kb)
; syntax:r2v16e <RAM addr>, <VRAM addr>, <number of bytes>
; modifies: AF,HL,DE,C
; note: **** INTERRUPTS MUST BE DISABLED ****
;
MACRO ram2vram17 ram,vram,num
ld a,vram >>>16
ld hl,vram & #FFFF ; 3/10 15/158
call SetVdp_Write
ld de,num ; 3/10
ld hl,ram ; 3/10
ld c,vdpport0 ; 2/7
.loop outi ; 2/16
dec de ; 1/6
ld a,d ; 1/4
or e ; 1/4
jp nz,.loop ; 3/10
endm
; fillvram17: fill VRAM (full 128Kb)
; syntax:r2v16e <VRAM addr>, <number of bytes>, >value>
; modifies: AF,HL,DE,C
; note: **** INTERRUPTS MUST BE DISABLED ****
;
MACRO fillvram17 vram,num,value
ld a,vram >>>16
ld hl,vram & #FFFF ; 3/10 15/158
call SetVdp_Write
ld de,num ; 3/10
ld c,vdpport0 ; 2/7
.loop ld a,value
out (c),a
dec de ; 1/6
ld a,d ; 1/4
or e ; 1/4
jp nz,.loop ; 3/10
endm
;----------------------------------
Nline equ 20
STRUCT line
Xorg db 0
db 0
Yorg db 0
db 1
Xdst db 0
db 0
Ydst db 48
db 0
XN db 64
db 0
YN db 6
db 0
db 0
db 0
db #D0
ENDS
;----------------------------------
startProgram:
ld a,#FF
ld (#F3E9),a ; FORCLR
xor a
ld (#F3EA),a ; BAKCLR
ld a,8
call #5f
ld a,1
call #5f
halt
scr4_init
page1
ram2vram17 (#F920),0,256*8
ram2vram17 (#F920),256*8,256*8
ram2vram17 (#F920),256*8*2,256*8
fillvram17 #2000,256*8*3,#31
fillvram17 128*256,128*96,r
fillvram17 #1800,256*3,' '
fillvram17 #5800,256*3,' '
di
vdpw 19,Nline*8-3
.loop
vdpw 15,1
wait_FH
vdpw 15,2
wait_hbl
scr5
ld hl,linepage1
ld de,(XY)
call plotscreen
scr4
page2
vdpw 15,0
call testdir
vdpw 15,1
wait_FH
vdpw 15,2
wait_hbl
scr5
ld hl,linepage2
ld de,(XY)
call plotscreen
scr4
page1
vdpw 15,0
call testdir
call testesc
jp nz,.loop
ei
xor a
call #5f
ret
;************************************************************
; Test if esc key is pressed.
; If pressed, z flag is positioned to 0
;************************************************************
testesc:
in a,(#aa)
and %11110000
add a,7
out (#aa),a
in a,(#a9)
and 4
ret
;*********************************************************
; I/O
;*********************************************************
testdir
ld a,8
out (#aa),a
in a,(#a9)
ld hl,X
.ri bit 7,a
jp nz,.le
inc (hl)
jp .up
.le bit 4,a
jp nz,.up
dec (hl)
.up ld hl,Y
bit 5,a
jp nz,.dw
rept 6
dec (hl) ; things are much trikyer than this
endm
.dw bit 6,a
jp nz,.fire
rept 6
inc (hl) ; things are much trikyer than this
endm
.fire ;bit 0,a
ret
;--------------------
XY:
X: db 0
Y: db 0
linepage1
line 0, 0, 0, 1, 0, 0
line 0, 0, 6, 1, 64, 0
line 0, 0,12, 1,128, 0
line 0, 0,18, 1,192, 0
linepage2
line 0, 0, 0, 1, 0, 0, 48+128, 0
line 0, 0, 6, 1, 64, 0, 48+128, 0
line 0, 0,12, 1,128, 0, 48+128, 0
line 0, 0,18, 1,192, 0, 48+128, 0
;--------------------
plotscreen:
ld c,vdpport3
vdpw 7,#3
rept 4
vdpw 17,32
ld a,e
add a,(hl)
out (vdpport3),a
inc hl
outi
ld a,d
add a,(hl)
out (vdpport3),a
inc hl
outi
dw #A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED,#A3ED
wait_CE
endm
vdpw 7,0
ret
;
;Set VDP port #98 to start writing at address AHL (17-bit)
;
SetVdp_Write: rlc h
rla
rlc h
rla
srl h
srl h
vdp 14 ;set bits 15-17
ld a,l ;set bits 0-7
out (vdpport1),a
ld a,h ;set bits 8-14
or 64 ; + write access
out (vdpport1),a
ret
endProgram:
END
| | manuel
msx guru
Berichten: 3447 | Geplaatst: 02 November 2005, 18:33 | Hi, sjasm crashes with a Segmentation Fault with your test2.asm....
Please send me a binary: manuel AT msxnet DOT org.
| | ARTRAG
msx master
Berichten: 1685 | Geplaatst: 06 November 2005, 18:29 | Hello Manuel!
the idea has become a working source!
With Magoo we have done a small vscreen level demo
you will find it very soon on vscreen web page
vscreen.hypercu.be
In order to unveil the solution for vertical scroll here follows
the CORE part of the code that is devolved to the rendering of
the screen.
Unfortunately this time you cannot just compile & run but you need
all the vscreen initializations and support routines.
Btw everything is ready and will soon appear at vscreen.hypercu.be.
Enjoy
; VDP ports
;
vdpport0 equ 098h ; VRAM read/write
vdpport1 equ 099h ; VDP registers read/write
vdpport2 equ 09ah ; Palette registers write
vdpport3 equ 09bh ; Indirect register write
;----------------------------------
Nline equ 24
;----------------------------------
startProgram:
di
scr4_init
page1
vdpw 19,Nline*8-3
.loop
call testdir
call display
; from here preserve hl and de
vdpw 15,1
wait_FH
vdpw 15,2
wait_hbl
scr5
call plotscreen
scr4
page1
vdpw 15,0
call testesc
jp nz,.loop
ei
jp ending
;;************************************************************
;; Test if esc key is pressed.
;; If pressed, z flag is positioned to 0
;;************************************************************
;testesc:
; in a,(#aa)
; and %11110000
; add a,7
; out (#aa),a
; in a,(#a9)
; and 4
; ret
;*********************************************************
; I/O
;*********************************************************
testdir
ld a,8
out (#aa),a
in a,(#a9)
ld hl,X
.ri bit 7,a
jp nz,.le
inc (hl)
jp .up
.le bit 4,a
jp nz,.up
dec (hl)
.up ld hl,Y
bit 5,a
jp nz,.dw
dec (hl)
.dw bit 6,a
jp nz,.fire
inc (hl)
.fire ;bit 0,a
ret
;*********************************************************
;
;Set VDP port #98 to start writing at address AHL (17-bit)
;
SetVdp_Write: rlc h
rla
rlc h
rla
srl h
srl h
vdp 14 ;set bits 15-17
ld a,l ;set bits 0-7
out (vdpport1),a
ld a,h ;set bits 8-14
or 64 ; + write access
out (vdpport1),a
ret
;*********************************************************
X: db 0
Y: db 0
;Input: D = Dividend, E = Divisor, A = 0
;Output: D = Quotient, A = Remainder
Div8:
xor a
rept 8
sla d
rla
cp e
jr c,$+4
sub e
inc d
endm
ret
;*********************************************************
;
; display the screen at coordinate X,Y in the logical map
;
; logical map : 128x256 stored in VRAM at #8000 (scr5 page 1)
; screen : 32x24 stored in VRAM at #1800 (scr4)
;
display
; e := (Y) mod 24
; a := (Y) / 24
ld a,(Y)
ld d,a
ld e,24
call Div8
ld c,a
ld b,0
; hl := offset[2*bc]
sla bc
ld hl,offset
add hl,bc
ldi bc,(hl)
ld hl,bc
; a: = d*24
ld a,d
add a,d
add a,d
rept 3
add a,a
endm
ld d,a
ld a,(X)
ld e,a
ret
offset
dw l01
dw l11
dw l21
dw l31
dw l41
dw l51
dw l61
dw l71
dw l81
dw l91
dw l101
dw l111
dw l121
dw l131
dw l141
dw l151
dw l161
dw l171
dw l181
dw l191
dw l201
dw l211
dw l221
dw l231
plotscreen:
ld c,vdpport3
rept 8
ld a,(hl)
cp -1
ret z
vdpw 17,32
out (c),e ; Xorg
out (c),0
ldi a,(hl)
add a,d ; multiplo di 24
out (vdpport3),a ; Yorg
ld a,1
out (vdpport3),a ; Yorgpage
outi ; Xdst
out (c),0
ldi a,(hl)
add a,48
out (vdpport3),a ; #1800 Ydst
out (c),0
outi ; DX
out (c),0
outi ; DY
out (c),0
out (c),0
out (c),0
ld a,#D0
out (vdpport3),a
wait_CE
endm
ret
l01
db 0,0,0,64,6
db 6,64,0,64,6
db 12,128,0,64,6
db 18,192,0,64,6
db -1
l11
db 1,192,0,64,5
db 6,0,0,64,6
db 12,64,0,64,6
db 18,128,0,64,6
db 24,192,5,64,1
db -1
l21
db 1,128,0,64,5
db 7,192,0,64,5
db 12,0,0,64,6
db 18,64,0,64,6
db 24,128,5,64,1
db 30,192,5,64,1
db -1
l31
db 1,64,0,64,5
db 7,128,0,64,5
db 13,192,0,64,5
db 18,0,0,64,6
db 24,64,5,64,1
db 30,128,5,64,1
db 36,192,5,64,1
db -1
l41
db 1,0,0,64,5
db 7,64,0,64,5
db 13,128,0,64,5
db 19,192,0,64,5
db 24,0,5,64,1
db 30,64,5,64,1
db 36,128,5,64,1
db 42,192,5,64,1
l51
db 2,192,0,64,4
db 7,0,0,64,5
db 13,64,0,64,5
db 19,128,0,64,5
db 24,192,4,64,2
db 30,0,5,64,1
db 36,64,5,64,1
db 42,128,5,64,1
l61
db 2,128,0,64,4
db 8,192,0,64,4
db 13,0,0,64,5
db 19,64,0,64,5
db 24,128,4,64,2
db 30,192,4,64,2
db 36,0,5,64,1
db 42,64,5,64,1
l71
db 2,64,0,64,4
db 8,128,0,64,4
db 14,192,0,64,4
db 19,0,0,64,5
db 24,64,4,64,2
db 30,128,4,64,2
db 36,192,4,64,2
db 42,0,5,64,1
l81
db 2,0,0,64,4
db 8,64,0,64,4
db 14,128,0,64,4
db 20,192,0,64,4
db 24,0,4,64,2
db 30,64,4,64,2
db 36,128,4,64,2
db 42,192,4,64,2
l91
db 3,192,0,64,3
db 8,0,0,64,4
db 14,64,0,64,4
db 20,128,0,64,4
db 24,192,3,64,3
db 30,0,4,64,2
db 36,64,4,64,2
db 42,128,4,64,2
l101
db 3,128,0,64,3
db 9,192,0,64,3
db 14,0,0,64,4
db 20,64,0,64,4
db 24,128,3,64,3
db 30,192,3,64,3
db 36,0,4,64,2
db 42,64,4,64,2
l111
db 3,64,0,64,3
db 9,128,0,64,3
db 15,192,0,64,3
db 20,0,0,64,4
db 24,64,3,64,3
db 30,128,3,64,3
db 36,192,3,64,3
db 42,0,4,64,2
l121
db 3,0,0,64,3
db 9,64,0,64,3
db 15,128,0,64,3
db 21,192,0,64,3
db 24,0,3,64,3
db 30,64,3,64,3
db 36,128,3,64,3
db 42,192,3,64,3
l131
db 4,192,0,64,2
db 9,0,0,64,3
db 15,64,0,64,3
db 21,128,0,64,3
db 24,192,2,64,4
db 30,0,3,64,3
db 36,64,3,64,3
db 42,128,3,64,3
l141
db 4,128,0,64,2
db 10,192,0,64,2
db 15,0,0,64,3
db 21,64,0,64,3
db 24,128,2,64,4
db 30,192,2,64,4
db 36,0,3,64,3
db 42,64,3,64,3
l151
db 4,64,0,64,2
db 10,128,0,64,2
db 16,192,0,64,2
db 21,0,0,64,3
db 24,64,2,64,4
db 30,128,2,64,4
db 36,192,2,64,4
db 42,0,3,64,3
l161
db 4,0,0,64,2
db 10,64,0,64,2
db 16,128,0,64,2
db 22,192,0,64,2
db 24,0,2,64,4
db 30,64,2,64,4
db 36,128,2,64,4
db 42,192,2,64,4
l171
db 5,192,0,64,1
db 10,0,0,64,2
db 16,64,0,64,2
db 22,128,0,64,2
db 24,192,1,64,5
db 30,0,2,64,4
db 36,64,2,64,4
db 42,128,2,64,4
l181
db 5,128,0,64,1
db 11,192,0,64,1
db 16,0,0,64,2
db 22,64,0,64,2
db 24,128,1,64,5
db 30,192,1,64,5
db 36,0,2,64,4
db 42,64,2,64,4
l191
db 5,64,0,64,1
db 11,128,0,64,1
db 17,192,0,64,1
db 22,0,0,64,2
db 24,64,1,64,5
db 30,128,1,64,5
db 36,192,1,64,5
db 42,0,2,64,4
l201
db 5,0,0,64,1
db 11,64,0,64,1
db 17,128,0,64,1
db 23,192,0,64,1
db 24,0,1,64,5
db 30,64,1,64,5
db 36,128,1,64,5
db 42,192,1,64,5
l211
db 11,0,0,64,1
db 17,64,0,64,1
db 23,128,0,64,1
db 24,192,0,64,6
db 30,0,1,64,5
db 36,64,1,64,5
db 42,128,1,64,5
db -1
l221
db 17,0,0,64,1
db 23,64,0,64,1
db 24,128,0,64,6
db 30,192,0,64,6
db 36,0,1,64,5
db 42,64,1,64,5
db -1
l231
db 23,0,0,64,1
db 24,64,0,64,6
db 30,128,0,64,6
db 36,192,0,64,6
db 42,0,1,64,5
db -1
endProgram
| |
| |
| |
