I could be wrong, but I think that some (maybe a long) time ago I heard something about the possibility of this type of implementation in a real MSX.

Note that there are more MSXes with RAM in slot 0, page 2 and 3. An example is the Sony HB-F500P.

It's a very interesing project. the most interesting part is the ability to achieve this on all msx'es and to overpower the gfx performances.
Cool the ability to execute z80 code from vram!
Cool the retained 100% compatibility of old vdp/vram interface
Cool the possibility to achieve more speed with a more speedy cpu (increasing clock, etc)

However:

Note also that the test program is created clearly to flavor z80:
- always byte aligned operations in modes different of screen 8
- screen 6 test are forbidden (has the more work to do to mask/unmask bytes)
- most test use screen 8 where 1byte = 1pixel and it's very easy to calculate vram address from x/y (simply store in HL)
- most test does not use trasparency to avoid in screen8 the reading and writing of vram (only a writing)
- Burst transfer operations, not rectangular based ones as more frequent in real world. (makes routines simpler)

doing exacly what the vdp does (including x,y in 16bit format, transparent format, logical operations, no byte aligned restrictions in logical operations, etc) will quickly degrade speed...

Could Ademir put the schematics on-line?

I wonder if he is not going to continue with the project, then someone else would like to do it...
Maybe implementation is not too complicated and a DIY article can be done ....

Is anybody in contact to Ademir?