Hello

I'm coding a game for the MSXDev'06. I'm using direct VDP access (so not SETWRT, LDIRVM, etc.) in some routines for speed. Can someone tell me how processor cycles have to occur between accesses to the VDP ?

For example, will this work on a real MSX1:

xor a
loop: out (98h),a
djnz loop

... or is it to fast ?

Since I don't have a real MSX anymore I've to develop and test with emulators (I mainly use BlueMSX). Does somebody here have a real MSX and live around Hasselt or Leuven, Belgium ? So I can try my game before I submit it to the MSXDev.

Thx

During the display period it is to fast, so you need to use a few (±2) NOPs aswell.

I've used this kind of loop several times and usually the time wasted doing DJNZ is enough to keep clean the output ( or at least in my HB-75P ). Of course if you want to be sure you can insert, as GhostwriterP says, no more than two NOPs.
Sadly, the emulators don't "emulate" such "feature".

thx for the replies.

If DJNZ seems to take long enough, then the 2 ex (sp),hl instructions in the BIOS are a bit of a time waste?

Except for initialisation of the VRAM, I'm doing all vdp accesses during the vertical retrace. Can I omit wait instructions during vertical retrace?

During vertical restrace you can lose the wait, DJNZ should be more than enough.
However outside this period use 2 additional NOPs, you must know an OTIR is also too fast.

...and yes, the 2 EX (SP),HL are a total waste of time; but when the BIOS was programmed the VRAM ICs are far slower than a few years later, so the programmers feel that is better to be cautious about that.

Even during the non-blank you can copy at the same speed without delays. I've been able to copy 3,5 KB (lower part of the screen) per frame at 50 Hz without introducing any delays, just a pure 3,5x1024 OUTI program block

Let me guess, you disabled the screen?

The time between two outs on the display area needs to be at least 28 z80 cycles, which means you can do e.g.

outi
nop
nop
outi
....

And yes, your loop is too fast, only 26 z80 cycles. Adding one nop in the loop is enough to make it work correctly.

If you modify your loop like this:

loop:
out($98),a
dec b
jp nz,loop

You'll get a loop that takes exactly 28 cycles and works the same as yours.

Quote:

The time between two outs on the display area needs to be at least 28 z80 cycles

Are the cycles spent doing the OUT a delay in itself?. In your loop, you get 28 cycles when OUT time is included...

P.D.: Ooops, one hundred posts, yay!

The out takes 11+1=12 cpu cycles on an MSX1 and MSX2 (on some MSX2+ and TR it takes 13 cpu cycles). If you write too fast, the VDP will not be able to process the data and you'll get corruption. So the outs doesn't get delayed (except on TR machines which iirc has some built in flow control and a small pipe in the S-1990 chip).

Ps. Oops, my 346th post Double yay !

Right, only TR machines have some kind of delay when doing OUTputs; but I mean if the 12 cycles of the OUT instruction must be considered as part of the 28T forced delay between VRAM accesses. I've always counted only the T-states of the instructions following the OUT...

The OUT is included in the sum of T cycles. In the loop the OUTs are emitting a byte every 28 T cycles, so that 28 T cycles between the beginning of 2 I/O writes. I don't know if this is okay for the VDP.

*EDIT*

I was quoting this one:

Are the cycles spent doing the OUT a delay in itself?. In your loop, you get 28 cycles when OUT time is included...



Another question: do the V9938 and V9958 require the same wait states ?

Quote:

In the loop the OUTs are emitting a byte every 28 T cycles

Seems logic... . So, using the fastest OUT, there's always a minimum of 12T delay and you only need to add 16T more to be sure when working with screen 1 and 2 (both need delays between 7T-28T).
As far as I know the VRAM in MSX2 and higher machines is buffered; so there's no need to delay the outputs. OTIR works fine in these machines!

Yes, the V9938 and V9958 doesn't have the same 'slow' reads from the bus as the V9918 and TMS video chips. There is probably a limit on how fast you can out things on an MSX2 or higher too but the real limit may be the speed of which the Z80 can output data on the bus.

Note though that the MSX1 VDP only require 28 T cycles on the draw area of the screen. On the top and bottom border you can out much faster. In the border scroller in MSX Unleashed, we out data as fast as possible, using code lile :

    out (c),b
    out (c),d
    out (c),e
    out (c),h
    out (c),l

to change the background color as fast as possible to do the 'pixel on' / 'pixel off' in the scroller. This only works in the border though.