Since some OCM are sold in japan there might be possible to catchthe VHDL source that is supposed to be deliver on the CD rom , has anybody seen it , somewhere ?

Bart: Edwin has a point. If there's no way to develop VHDL on Linux, it could mean that he is not interested in buying an OCM.

So, how do we develop VHDL for OCM under Linux? It's still a damn valid question.

Is something like the "Icarus Verilog Compiler" useful?

Can't you just wine the compiler?

Wine does not appear to be an option. The application database says that a few parts of it work (sometimes), but the synthesis module is not mentioned as working. I'm hoping to run into the full linux somewhere by "accident".
Maybe the search for an alternative should be moved to new thread.

Xilinx proposes on th web , for free , its vhdl compiler for xilinx fpga : ISE .
And a limited licence for modelsim (simulator) I use them both on XP.
ISE works on linux for sure , and maybe modelsim.

I'd love to see an EASY crash-course on VHDL. In Brazil there are a very cheap starter kit using Xilinx chips (www.aee.com.br) and it would help a lot the development of the open-source one-chip-msx. All the VHDL blocks are around, just need someone with enough VHDL knowledge to gather the info and build the thing. Dal Poz also already made his implementation. What is missing here?

Edwin, please check out that link: http://www.symphonyeda.com/

Hey, this looks interesting. Is the FREE edition all you need to modify existing VHDL, compile it and put back in the OCM?

Nice program Tanni! I installed the free edition and seems more accessible than some of the others.

Manuel: unfortunately it is not enough as it doesn't do synthesis. So far I haven't found anything that can fill the whole chain from vhdl to the OCM. Although I would be very happy if Tanni could prove me wrong on that.

Edwin, actually, I never used or even downloaded that! The link was provided by another tutor in one of the practicals I also was tutor. At that time, I didn't have a computer to run it!

Manuel: For actually modifying the OCM functionality, you will have to use the software provided by Altera. The link to symphonyeda is just for having a VHDL compiler available to thouse who really want to learn VHDL to use the time until the OCM is released. If someone is really interested in modifying the OCM code, I strongly recommend to begin to learn VHDL now, starting with simulations of e.g. basic gates like that in the first posting of that thread. If you try to do just some modifications of the OCM code without really knowing what you do, you will most certainly fail. Before I was tutor, I passed a FPGA-practical using VHDL by my own. This practical was about one university term. The first half of the term, we did several small VHDL desings, e.g. a Smith-Waterman cell or some components leading in a shooting game like the ones first came out in the seventieth. It's relatively easy to do that, but it need some weeks of work. Unfortunately, the game I coded never worked correctly. The second half of the term, we had to choose a project by our own. There were several proposals of projects, but we also could select a project we like. I have choosen to implement a very very small ARAM with some processing functionality. ARAMs need exponential space, so I only had one variant with 4 bit bitvectors and more functionality and one with bitvectors of 8 bit length and limited functionality. At the end of the term, we should do a presentation of our project. We were recommended to have a variant, so we could present another design in case the original project design wouldn't work. I prepared this second piece of code some days before presentation. It worked very well at that time. My principal variant did not work in the way I intended until presentation, and I didn't know why. So I first had to show the other design. But it didn't load! I tried it serveral times, but the downloading always failed! Than, the assistant took the other board I used during preparation. The presentation took place in a room beside the room I did my work. He said, that possibly the download problems occure because of the different temperatures of the device. Fortunately, the bitstream did load with the FPGA device from the other room. It ran perfectly. After that, I again tried to download the original project. It worked, too, but didn't perform the full funtionality. After the presentation, I did some debugging and found out the reason why the first project didn't work the way I intended: To save some time while compiling for testing, I commented out parts of the code I didn't like to test at that time. I forgot that and so this functionality couldn't work, of course. This is for showing that doing VHDL -- or other HDL-coding -- isn't just like ordinary software-coding, even if it looks like that.

Quote:

ARAM

What's that?

ARAM = Associative RAM

The memory consists of a bitverctor called flagvector, where there is a flag for every number in a certain range. If the size of the flagvector is about 4 bit, you only can have 4 numbers in the memory, usually 0, 1, 2, and 3. If e.g. flag 0 is set, that means that number 0 is in the memory. If non of the flags are set, the memory is empty. If all of them are set, every number -- here 0, 1, 2, and 3 -- are in the set. With this kind of representation, you are able to perform lots of computation, e.g. arithmetical or logical operations or set operations e.g. IN, INSIDE or OUTSIDE certain borders, lower or higher a certain value in ONE clock cycle on ALL of the values within the flagvector SIMULTAEOUSLY! I implemented tow logical operations AND and OR, if I remember correctly, and two arithmetical operations, DIV and MOD. This operations are -- believe it or not -- relatively easy to implement, at least if the amount of numbers is very small. Note that such an approach works highly in parallel. My VHDL design showed the flagvectors -- besides others -- when the electron beam was in the visuable screen scope and did the parallel computation on all of the 4 or 8 bits of the flagvector respectively during one clock cycle in the blanking interval of the VGA control. For the game, it was nescessary to make a VGA control in VHDL. The Xilinx FPGA device used had only about 400 CLBs.

Quote:

ARAM = Associative RAM The memory consists of a bitverctor called flagvector, where there is a flag for every number in a certain range. If the size of the flagvector is about 4 bit, you only can have 4 numbers in the memory, usually 0, 1, 2, and 3. If e.g. flag 0 is set, that means that number 0 is in the memory. If non of the flags are set, the memory is empty. If all of them are set, every number -- here 0, 1, 2, and 3 -- are in the set.

Sounds like something that could be useful for quantum computing or genetic programming