MSX Assembly Page

wow, there is the "Mystery fast loop calculus"
no more LD A,B : OR C , 16bit loop fullsped.
sometimes one has conditional exit and would like to have BC back like it would normaly have counted, what is the reverse mystery formula?
DEC B : DEC C : INC BC, would this work?

I improved the explanation of R800 timing information in the Z80 instruction set overview article, as well as added a new column with actual R800 timing in internal RAM mode.

The timings in the table are based on research by the openMSX team and verified by myself using a different, cycle-accurate methodology.

The testing methodology I used is as follows: I have an OPL4 wave register write routine which requires at least 8 clocks between I/O instructions. One is used for a register load, the remaining 7 clocks need to be spent waiting. By using these instructions for waiting followed by a variable number of 1-cycle nop delays, I was able to acquire cycle-accurate timing information.

A few I didn’t test explicitly, because they were so similar to ones tested previously that I felt confident to copy their timing, e.g. push bc vs. push de. The results are overall quite consistent, although I was a bit surprised by ret taking only 5 clock cycles.

There are a few remaining, which I will get to later. I need to adjust my testing methodology to be able to test them (read: use OPLL in stead of OPL4).

I see a little mistake.

QUEUES #F3F3 Address of the queue table for PLAY instruction

FRCNEW #F3F5 Work aera size for PLAY instruction (255 by default)

http://map.grauw.nl/resources/msxsystemvars.php

I’ve completed the R800 timing information, except for the repeat-instructions which take too long for me to capture accurately with my testing method. I hope you enjoy it.

thanks!
very good