turbo R support

By flyguille

Prophet (3031)

25-04-2004, 21:06

i need a image of the routine than do the switching to the turbo mode.

to ENABLE and to DISABLE.

for support that on mnbios.

By Sonic_aka_T

Enlighted (4130)

30-04-2004, 20:41

Try disassembling the Turbo-R's BIOS. Remember that apart from standard R800 mode there's also R800 DRAM support which will be a lot faster, especially in BASIC. Just download the ROMs from any emulator site and follow the routine that starts at $0180 of the main BIOS entry. Bit 7 controls the R800 LED on the front, bits 1 and 0 control the CPU setting, R800 ROM and R800 DRAM mode. With bits 1 and 0 cleared you switch back to Z80.

By Sonic_aka_T

Enlighted (4130)

30-04-2004, 20:57

Well, here you go... How nice am I huh? Though maybe someone has their own routine. It looks like this BIOS version may have a little overhead... But anyways... It's a start at least... Just make whatever modifications you see fit and check on NLMSX or something to see if it still works...

$0180             JP    $046A

$0468   F1        POP   AF
$0469   C9        RET
$046A   F5        PUSH  AF
$046B   E67F      AND   $7F
$046D   FE03      CP    $03
$046F   30F7      JR    NC,$0468
$0471   F1        POP   AF
$0472   F3        DI
$0473   E5        PUSH  HL
$0474   D5        PUSH  DE
$0475   C5        PUSH  BC
$0476   F5        PUSH  AF
$0477   DDE5      PUSH  IX
$0479   FDE5      PUSH  IY
$047B   D9        EXX
$047C   08        EX    AF,AF
$047D   E5        PUSH  HL
$047E   D5        PUSH  DE
$047F   C5        PUSH  BC
$0480   F5        PUSH  AF
$0481   ED57      LD    A,I
$0483   F5        PUSH  AF
$0484   ED73FDFF  LD    ($FFFD),SP
$0488   08        EX    AF,AF
$0489   E683      AND   $83
$048B   4F        LD    C,A
$048C   0600      LD    B,$00
$048E   21B1FC    LD    HL,$FCB1
$0491   7E        LD    A,(HL)
$0492   CB21      SLA   C
$0494   CB8F      RES   1,A
$0496   2002      JR    NZ,$049A
$0498   CBCF      SET   1,A
$049A   3006      JR    NC,$04A2
$049C   CBBF      RES   7,A
$049E   2802      JR    Z,$04A2
$04A0   CBFF      SET   7,A
$04A2   77        LD    (HL),A
$04A3   D3A7      OUT   ($A7),A
$04A5   21E304    LD    HL,$04E3
$04A8   09        ADD   HL,BC
$04A9   3E06      LD    A,$06
$04AB   D3E4      OUT   ($E4),A
$04AD   DBE5      IN    A,($E5)
$04AF   04        INC   B
$04B0   CB6F      BIT   5,A
$04B2   2801      JR    Z,$04B5
$04B4   04        INC   B
$04B5   0EE5      LD    C,$E5
$04B7   EDB3      OTIR
$04B9   F3        DI
$04BA   00        NOP
$04BB   ED7BFDFF  LD    SP,($FFFD)
$04BF   F1        POP   AF
$04C0   ED47      LD    I,A
$04C2   F1        POP   AF
$04C3   C1        POP   BC
$04C4   D1        POP   DE
$04C5   E1        POP   HL
$04C6   D9        EXX
$04C7   08        EX    AF,AF
$04C8   FDE1      POP   IY
$04CA   DDE1      POP   IX
$04CC   F1        POP   AF
$04CD   C1        POP   BC
$04CE   D1        POP   DE
$04CF   E1        POP   HL
$04D0   FB        EI
$04D1   C9        RET
$04D2   3E06      LD    A,$06
$04D4   D3E4      OUT   ($E4),A
$04D6   DBE5      IN    A,($E5)
$04D8   E660      AND   $60
$04DA   87        ADD   A,A
$04DB   87        ADD   A,A
$04DC   3E00      LD    A,$00
$04DE   C0        RET   NZ
$04DF   3C        INC   A
$04E0   D8        RET   C
$04E1   3C        INC   A
$04E2   C9        RET
$04E3   60        LD    H,B
$04E4   60        LD    H,B
$04E5   40        LD    B,B
$04E6   60        LD    H,B
$04E7   00        NOP
$04E8   60        LD    H,B
$04E9   00        NOP
$04EA   00        NOP
$04EB   00        NOP
$04EC   00        NOP
$04ED   00        NOP
$04EE   00        NOP
$04EF   00        NOP

By BiFi

Enlighted (4348)

30-04-2004, 21:18

Nice... Now explain what happens.

By flyguille

Prophet (3031)

30-04-2004, 21:27

for what is that array?
how works that I/O ports E4 or E5? that are the s1990?

FCB1 address?
A7 I/O?

By BiFi

Enlighted (4348)

30-04-2004, 21:41

Sonic, you wanna do the honours explaining all this?

By flyguille

Prophet (3031)

30-04-2004, 21:51

all push / pops and SP,(FFFD) are for save al regs value of the one CPU. I know that

buy why a arraY?, how works that I/O? how work the I/O data from/to the routine?

By BiFi

Enlighted (4348)

30-04-2004, 22:05

that array, as you call it, is a table containing the data values for the various CPU mode settings. The data is made in pairs. The first is the actual CPU setting, the second is some kind of timer to duplicate the program counter. That way the other CPU knows where to continue.

I/O port $E4 is set to the CPU mode register in the S1990. I/O port $E5 is written with the CPU mode data.

Address $FCB1 contains the value that is written in I/O port $A7 since it's a write-only port. The port contains a bit that controls the Turbo LED.

By Sonic_aka_T

Enlighted (4130)

30-04-2004, 22:22

Your guess is a good as mine... Trust me, I don't have an R800 technical data book in Enlish lying around somewhere The OUTs are done to actually switch CPU. It would just be a matter of tracing the code to see which out does what. Just fill in each possible value for A and see what the code would actually do.

The OUT to $A7 controls the R800 led. The $FCB1 address stores the state of the processor (bit1 = Z80) and the state of the led (bit7 = on). What the actual OUTs to $E5 do I don't know, like I said; I don't have the technical data book What matters tho, is that it works which is as far as I can get you....

You asked for a CPU switching routine, this is one. For detailed info on the Engine and the R800 you would prolly have to contact ASCII I *think* I heard Arjan Bakker from Team Bomba say once he had a CHGCPU routine. Maybe he knows what the OUTs actually do. Try asking him, perhaps he knows what goes on in the little engine that could...

Good luck...

By flyguille

Prophet (3031)

30-04-2004, 22:39

LD a,00
JP 0180
what do?

LD a,01
jp 0180
what do?

ld a,02
jp 0180
what do?

By snout

Ascended (15187)

30-04-2004, 22:41

Ah wait, I know that one

LD a,00
JP 0180

Z80 mode

LD a,01
JP 0180

R800 ROM mode

LD a,02
JP 0180

R800 DRAM mode

yay!

(it was correct, wasn't it? )