An sketch of a protocol, inspired in CAN with two data lines on trigger pins (6,7) and a third bidirectional data line (ATT) made out of a diode from pin 8 to pin 1.
This bus Idles with both data lines in HIGH and the ATT line in LOW.
The station who wants to transmit, drop both data lines and releases its ATT line, then wait for all the stations to release their ATT lines which can be recognized by the ATT line going High. This marks the end of the SYNC phase. After that, station 1 starts to transmit its address.
In the example, Station 2 have data to transmit, and after recognize the end of the SYNC phase it start to transmit its address.
The address is put on the DATA lines at the same time the ATT line is held down, and then the sender rises its ATT line and waits for the the level on ATT line to go high, then sample the resulting value (Y0/Y1, Y2/Y3....
The senders must compare the values written on the bus (D0/D1, D2/D3....) with the values read back (Y0/Y1, Y2/Y3....) to check if they won the arbitration. The one with smaller ID wins. This is done every 2 bits of addressing.
The station who won the arbitration keeps sending addressing data, while the one who lost the arbitration enters in "listen mode", while releasing the levels on its data line.
After the Addressing phase, the data are sent at every change of the ATT line, commanded by the station who won the arbitration. The example shows 2 bytes of data for didatic purposes.
At the end of the packet the sender releases its data lines and hold down the ATT line, returning the bus to Idle state.
After that, Station 2 that still have data to transmit, can initiate another bus cycle.
