FDD/service test cartridges?

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By Jipe

Paragon (1434)

Jipe's picture

18-01-2021, 07:58

can you make a picture of the other side please

By gdx

Prophet (4035)

gdx's picture

18-01-2021, 08:57

The metal bar doesn't cause short circuit?

By hap

Paragon (2032)

hap's picture

18-01-2021, 15:51

I don't see any bankswitch from looking at MSX1 STC schematics.
By writing 1 (OUT opcode) to 0x00-0x7f, the ROM can be disabled. It is enabled at power-on reset.

By Bas040

Master (196)

Bas040's picture

18-01-2021, 18:21

@gdx It's part of the movable protection of the cartridge inlet. I came loose after opening the cartridge case.

Picture of the other side:

By Jipe

Paragon (1434)

Jipe's picture

18-01-2021, 20:06

thanks Wink

By Jipe

Paragon (1434)

Jipe's picture

19-01-2021, 13:54

I checked the circuit and just added some few modification on schematic
the common of RA is Vcc +5v
adress for eprom is A0 toA13
on 74LS74 Vcc is pin 14 Gnd is pin 7

On the rom i can see this commands :
COMINI
ECOMDTR
OFCOMSTAT
FCOMBREAK
FCOMTERM
FCOM
GICOMON
ICOMOFF
ICOMSTOP

same as RS232 ??
BASS can you make a new copie of the eprom please

By calderone

Resident (36)

calderone's picture

19-01-2021, 20:53

Many thanks Bas040 for these detailed pictures !

If I check my previous proto board with this layout, I can see the following 'EXTRA' details/differences:
- same as Jipe, RA is connected to +5V
- same as Jipe, address for eprom is A0->A13
- on the Eprom, PIN27 (expected) but also PIN1 (VPP) is connected to +5V (not floating).
- on the 74LS74, PIN10->PIN14 are all connected to +5V
-> is this also to exclude floating inputs ??? Can this interfere if not connected ?
- no caps
- Eprom is an AMD 27128A-4DC
-> I'm now using a TMS 27C128-15JL on my proto board, would this give timing problems?
(need to check the datasheets, I suppose)

I will make some changes to my protoboard and test it again.

Also some more questions arise:

- Are the resistors 15k ?
- It seem, D0 enables the eprom through the 74LS74 flipflop !!? Not sure how this works.
When I look at the truth table I conclude (PR = always HIGH):
/CE is low at RESET and when D0 is LOW
So the eprom will work when D0 is LOW
Also A15 need to be LOW to enable the eprom, meaning all addresses below 32768 will trigger the eprom (and D0 LOW)
Can someone explain how this works ? Why D0 ?
- /WR, A7, /IORQ is used to generate some clock signal, I believe I can find other examples on the internet

To be continued ....

By hap

Paragon (2032)

hap's picture

19-01-2021, 21:36

7474 works as a 1-bit latch, the OUT opcode I mentioned before clocks(aka strobes) the 7474 and sets Q to D0 of the written value.

By calderone

Resident (36)

calderone's picture

20-01-2021, 11:21

@hap
Thanks, I believe I can understand your explanation now.
The ROM is enabled at power-on reset, also D0 should be LOW at reset. So the ROM is enabled indeed.
Then after that, D0 can be HIGH or LOW, it does not matter any more, as Q will keep the previous state (which is LOW) because PR is always HIGH.

By calderone

Resident (36)

calderone's picture

20-01-2021, 11:24

@Jipe
You mean, the listed ROM image might not be the correct one ? You suspect the ROM image is for a serial interface cartridge or so ?

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