create a megarom switching off the bios?

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Par thegeps

Paragon (1035)

Portrait de thegeps

08-02-2022, 14:57

I managed to switch RAM to page0, with my own ISR and keeping few routines (like gtstck, gttrig and snsmat wich I use in my code). I had some issues in the beginning, before understanding that I should ​had to hardcode "jp addresses" to get them working...

But then I realized that in this way 16Kb machines couldn't run Turrican (before switching RAM to Page0 it worked fine on Sony HB10, for example) because in my code I have RAM on page3 too... So I think I won't use it to grant compatibility to all MSX machines

Par Grauw

Ascended (10605)

Portrait de Grauw

08-02-2022, 15:15

Nice that you got it to work, but also nice that you’re considering the machines with less than 64K RAM Smile. There’s quite a few of them, e.g. the Yamaha CX5M has 32K.

Par thegeps

Paragon (1035)

Portrait de thegeps

08-02-2022, 15:39

Well, I'll use a megarom, and actually the code works fine. I won't break support for some msx only to gain few cycles from a rewritten isr. I'm not in need of RAM at the moment: actually I use less than 4KB of RAM. I stull have to write event check engine and surely I'll need RAM to store breakable/collectable objects and enemy tables, but hopefully I'll manage to fit them in page2. Any suggestion? LoL

Par Bengalack

Hero (594)

Portrait de Bengalack

08-02-2022, 18:23

Grauw wrote:
lister_of_smeg wrote:
Grauw wrote:

Or use WRSLT to poke a jp continue_address at RAM addresses 0-2, and then CALSLT to address 0 of the RAM slot.

If you preload hl (assuming you don't need to pass something using hl) with continue_address before CALSLT you only need put a jp (hl) at address 0.

Oh, nice one, that’s even more elegant!

Agree - all this is really neat and clever! Take note everyone Smile

Par sdsnatcher73

Prophet (3413)

Portrait de sdsnatcher73

08-02-2022, 18:30

thegeps wrote:

Well, I'll use a megarom, and actually the code works fine. I won't break support for some msx only to gain few cycles from a rewritten isr. I'm not in need of RAM at the moment: actually I use less than 4KB of RAM. I stull have to write event check engine and surely I'll need RAM to store breakable/collectable objects and enemy tables, but hopefully I'll manage to fit them in page2. Any suggestion? LoL

Couldn’t your ISR be in page 2? (Sorry if this is a stupid question, not a programmer on MSX). Or is it really necessary to remove the entire BIOS to replace the ISR with your own? My gut says it should not be that way (my gut is often right, obviously not alwaysWink)

Par thegeps

Paragon (1035)

Portrait de thegeps

08-02-2022, 19:54

sdsnatcher73 wrote:

Couldn’t your ISR be in page 2? (Sorry if this is a stupid question, not a programmer on MSX)

Not a stupid question Wink
A routine "hooked" to the isr can be everywhere, but the isr is triggered by the only interrupt we have on msx1, the vdp one. Wich is directly connected to the Z80 interrupt pin. When triggered it starts the code written at addres 38h (wich is in page0). So, if you want to get rid of all the accessory code that the bios isr execute (like reading keyboard, joystick, checking if there is a basic "on interval: trap and so on..) and even gain more few cycles avoiding to push/pop all unused registers in your code (like the shadow registers) you need to disable bios and put your own isr routine at 38h...

Well, now that I'm here talking about this...
Anyone, is it possible to discard page3 and set RAM on page0 so it can be done for 16KB MSX too?

Par ARTRAG

Enlighted (6846)

Portrait de ARTRAG

08-02-2022, 19:58

Actually you can change interrupt mode in the z80 and use register I to aim to a table of 257 addresses to prevent unknown values on the data bus.
So, if you accept to spend 257 bytes and to put your isr at a location whose address has its low byte equal to its high byte you can

Par ARTRAG

Enlighted (6846)

Portrait de ARTRAG

08-02-2022, 20:11

IM2 interupt mode makes the z80 jumps to I*256+databus

Usually one can put at the address aimed by I*256 257 repeated bytes in order to form an address with low byte equal to high byte e.g. 8080h independently by the value on the databus

Par Grauw

Ascended (10605)

Portrait de Grauw

08-02-2022, 20:10

thegeps wrote:

Anyone, is it possible to discard page3 and set RAM on page0 so it can be done for 16KB MSX too?

No, impossible.

Par aoineko

Champion (489)

Portrait de aoineko

08-02-2022, 21:58

I imagine that for a good electronician, it should not be very complicated to create a ROM with a mapper that spans the first 3 pages of memory space (address 0000h~BFFFh) with 3 banks of 16KB or 6 banks of 8KB.

It's not a "standard" mapper but if a good MSX game is released with this format, I imagine that emulators still in development should quickly add support for this format.

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