Does the enabling of the /WAIT signal slowdown the V9958?

Even with /WAIT signal activated, Z80 has to "wait" from time to time, after sending some bytes to VDP. This is one known issue.

Another issue is that working at 3.5 Mhz, buffers are capable to handle data speed from Z80 to VDP but, at 7 Mhz, buffers ships (74244, 74245 )are not able to handle speed properly so, turbo kits usually slow down speed to 3.5 Mhz when OUTing.
This can be fixed (or not) changing buffers with some faster (series HCT could be suitable).

Isn't there a longer delay needed, between setting VRAM read/write address & first data read/writes? Like: set address -> 'long' delay -> send 1st byte -> 'short delay' -> send 2nd byte -> 'short' delay -> send 3rd byte etc. Maybe that is what's causing VRAM corruption here?

Another issue is that working at 3.5 Mhz, buffers are capable to handle data speed from Z80 to VDP but, at 7 Mhz, buffers ships (74244, 74245 )are not able to handle speed properly so, turbo kits usually slow down speed to 3.5 Mhz when OUTing.
If the machine is an original MSX2+, chances are there aren't any buffers in the databus (highly integrated engine IC -> few IC's connected to databus -> no buffer IC's needed). Btw: 74HCT series is about as fast as 74LS series, if faster is needed you're looking at logic families like 74F, ALS or ACT series.

Usually this is not a problem with turbo circuits, they slow down for I/O requests exactly to avoid problems like the above, because most slow peripherals have in common that they are accessed via I/O ports. Switching clock back to 3.58 MHz temporarily is easier than adding wait cycles, because number of wait cycles to add would depend on each peripheral & turbo clock frequency.

You could switch back clock frequency with VDP's /CSR & /CSW signals, that way VDP is accessed at 3.58 MHz, but other I/O can be @turbo speed.

dont the vdp generates 3.5Mhz cpu clock?
i mean the wait signal generated by vdp might be intended to be used with that clock.
there might be some synchronous constraints between wait vdpclk and cpuclk they cant be totally out of phase ?
in other words building 7Mhz from vdpclk could help ?

Maybe for the TMS9918 and V9938 this is true, but on the V9958 the CPUCLK generation can be disabled (R#25, bit5) and then the pin-8 will output /VDS instead. This means this VDP must have been designed with I/O independent of that CPUCLK. This is probably the reason why they added the /WAIT output on pin-26: Exactly to allow turbo machines to be built. Turbo machines wouldn't need the CPUCLK signal and should rely on the /WAIT signal for I/O. Otherwise, why would the 3.5MHz Z80A need the V9958's /WAIT signal anyway, as it isn't fast enough to ever activate it?

i read on the v9958 datasheet that the wait signal is asserted 130ns after /CSW or /CSR is asserted.

but z80 sets /iorq + /wr or /rd + adress on the falling edge of t1 cycle cycle.
and samples wait line at the falling edge of t2 .

so there is one cycle of cpu clk : from falling t1 to falling t2 to do adress decode + 130ns of wait delay.

typically you may put 30ns for logic of decode 30 ns for wires delay and 130ns=190ns , so te wait
signal cant be used above 5.xx Mhz

an other option is to generate an unconditional wait signal with m1 cycle and "AND" it with the late
wait signal from VDP. like this it may work even 7Mhz

when you say you put the wait signal on z80 you added it with some AND function with the existing one build from M1 cycle ?

I fed the V9958's /WAIT signal to a 74LS07 and the output of this chip to the /WAIT line of the BUS. I added a 10K pull-up to the V9958's /WAIT pin as shown on the ExpertTurbo schematics.