VDP Status register , what do i miss here?

cool thanks for this tip i will study this.

Thank you again for your response.

Because i am using SDCC for my little project, i am still troubling with doing this the easy way. IM2 is kinda tricky in my current "workflow".

Polled timing:

__ASM

ei
halt 

__ENDIF

Works fine for me to run the code on timed, but i wanted to disable the system interrupts temporary.

I took ROADFIGHTER rom and had a look how konami did it.

They basically hook the whole game on HKEYI. They use a trick for not allowing the system to continue with HTIMI and updating the rest of the system.
Just before they return from HKEYI hook they add:

call 013e

So i guess this is a trick to fool the bios that the vdp didnt generate the interrupt

bios part:

0C3C:   push   hl         
0C3D:   push   de         
0C3E:   push   bc         
0C3F:   push   af         
0C40:   exx               
0C41:   ex     af,af'     
0C42:   push   hl         
0C43:   push   de         
0C44:   push   bc         
0C45:   push   af         
0C46:   push   iy         
0C48:   push   ix         
0C4A:   call   #fd9a      
0C4D:   in     a,(#99)    
0C4F:   and    a          
0C50:   jp     p,#0d02    
0C53:   call   #fd9f      

---
slowing down system stuff here
...

0D02:   pop    ix         
0D04:   pop    iy         
0D06:   pop    af         
0D07:   pop    bc         
0D08:   pop    de         
0D09:   pop    hl         
0D0A:   ex     af,af'     
0D0B:   exx               
0D0C:   pop    af         
0D0D:   pop    bc         
0D0E:   pop    de         
0D0F:   pop    hl         
0D10:   ei                
0D11:   ret               

I still dont know how to refer to direct (dynamic) address in SDCC on an interrupt, this looks like a solution for now.

Hope to release my little project soon, working more then a year on this... Yes i suck.

Eugeny, the device vector always comes to D[7 : 0] on the interrupt vector request -> !M1 & !IORQ.

Z80 address bus is either output or tri-stated.

@Wlcracks
BEWARE of Z80 and its clones fetching the interrupt table content from ODD addresses when supplied with the ODD vector on the data bus. Z80 manual is mute about it and emulators often ZERO the address bit 0, which is wrong. The real Z80 and its clones take the ODD table entry (0xFF in the LSB) and continue to the next address for the MSB for the jump address fetch when provided with 0xFF on the data bus.
Regarding the ODD device vector address (forbidden combination for the normal CPU operation) here are a few considerations:
- MSX1/2/2+ has historically the pull-up resistors on the databus. I.e. any I/O read yields 0xFF. However, the device vector address must be EVEN, but since 0xFF is returned on an empty data bus it will be ODD. Therefore the ISR address will be fetched from :
LSB is fetched from (I_reg<<8) + 255
and MSB is fetched from (I_reg+1)<<8, where I_reg is the I register.

Bottom line: if the data bus state is unknown and/or it's necessary to get the code running on ANY MSX machine, the ISR vector table MUST have not only 257 entries, but also the SAME MSB and LSB for the interrupt vector routine (required to cover the odd/even case on the data bus). For example, the interrupt vectors like 0xFEFE, 0xFDFD, 0xC1C1 are completely valid since MSB=LSB.