VHDL code for 4 x 4 register file (replacement fopr 74LS670 logic)

Por lkpalwa

Expert (114)

imagem de lkpalwa

19-01-2022, 18:49

Hi does anyone have the code for that, searching web, bud bad luck Sad
I have seen that some guys made it work when doing mappers, see this:

https://m.blog.naver.com/PostView.naver?isHttpsRedirect=true...

Erikie is he still active in the MSX world?

Found some code for it but does not compile, in Quartus2 I get errors

Error (276000): Cannot synthesize initialized RAM logic "SN74XX670:inst|regs"

and it point into init part of code:

signal regs : nibble_array := init;

function code is:

function init return nibble_array is
variable result : nibble_array;
begin
for i in nibble_array'range loop
result(i) := "0000";
end loop;
return result;
end function;

Thx in advanced :)

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Por Pencioner

Scribe (1502)

imagem de Pencioner

19-01-2022, 19:59

Old Quartus wouldn't understand function statements (they were added to VHDL after that). You have to unroll them to regular statements manually

Por lkpalwa

Expert (114)

imagem de lkpalwa

19-01-2022, 21:29

How do you mean? I running Quartus2 version 13.0sp1? Is function statement not allow in code?
Need to use that version to handle MAX 7000S chipset

Thx in advance! Smile

Por lkpalwa

Expert (114)

imagem de lkpalwa

19-01-2022, 21:37

functions where added in VHDL-93 or am I wrong ?

Sad

Por Pencioner

Scribe (1502)

imagem de Pencioner

19-01-2022, 21:46

Well, version 13 seems to support that (i tried it once with version 9.1 or so and it was not available)

What i found: https://www.intel.com/content/www/us/en/programmable/quartus...
so it seems like the code you found is not really synthezable (it might be only for emulation in tools but not for real chips). I guess you'd need to read coding styles mentioned in this link etc and change the code. Or maybe write your own

Btw with some googling i have found the implementations which implements 4x4 register file though they are not 3-state (so this should be modified to be fully equivalent to LS670) - http://quitoart.blogspot.com/2017/09/fpga-vhdl-verilog-4-bit...

Por lkpalwa

Expert (114)

imagem de lkpalwa

19-01-2022, 22:34

Yepp, I found that also but you get 2 ouput vectors of 4..0, the 74ls670 have only 1 ouput of 4..0 with 3 state, hmm need to look deep into the VHDL books Smile
Thx Smile

Por Pencioner

Scribe (1502)

imagem de Pencioner

20-01-2022, 00:22

I have sent a good reading to you by email Smile

Por lintweaker

Champion (437)

imagem de lintweaker

20-01-2022, 08:13

Note sure what Pencioner sent but this might be of help:
https://www.nandland.com/vhdl/examples/example-array-type-vhdl.html

Por WORP3

Paladin (861)

imagem de WORP3

20-01-2022, 13:13

You can use just basic VHDL, something like here below. just a rough and quick write down, so some typo's can be present:

signal DataIn: 	std_logic_vector(3 downto 0);
signal DataOut:	std_logic_vector(3 downto 0);
signal Reg1: 	std_logic_vector(3 downto 0);
signal Reg2: 	std_logic_vector(3 downto 0);
signal Reg3: 	std_logic_vector(3 downto 0);
signal Reg4: 	std_logic_vector(3 downto 0);
signal Wsel: 	std_logic_vector(1 downto 0);
signal Rsel: 	std_logic_vector(1 downto 0);
signal Wr:		std_logic;
signal Rd_en:	std_logic;

	DataOut <=	Reg1 when (Rsel="00") else
				Reg2 when (Rsel="01") else
				Reg3 when (Rsel="10") else
				Reg4 when (Rsel="11");

Process(clk,reset)
begin
    if (Reset = '1') then
	  Reg1 <= (others => '0');
	  Reg2 <= (others => '0');
	  Reg3 <= (others => '0');
	  Reg4 <= (others => '0');
    elsif (CLK 'event and CLK='1') then
      if (WR='1') then
		  case (Wsel) is
			when "00"   => Reg1 <= DataIn;
			when "01"   => Reg2 <= DataIn;
			when "10"   => Reg3 <= DataIn;
			when "11"   => Reg4 <= DataIn;
		  end case;    
      end if;
end process;

Por WORP3

Paladin (861)

imagem de WORP3

20-01-2022, 13:47

Programming FPGA's has nothing to do with actual programming, it's describing a digital design, so think like this:

Por lkpalwa

Expert (114)

imagem de lkpalwa

20-01-2022, 15:06

I think the issue is that the CPLD, MAX7000 (that is the case with MAX10 chips) does not support memory initialization, but maybe it works anyway because in the original code we always starts with ZZZZ, and initial a WE will be done before a RE, to add the data from ROM to RAM, will try on and hopefully it works Smile

Thx for all the input Smile