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Toshiba T7937
This page was last modified 18:27, 8 March 2023 by Mars2000you. Based on work by Gdx and Acet and others.

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Description

Toshiba T7937

The Toshiba T7937 is a chipset called MSX-ENGINE designed for MSX1 systems with the following features:

In fact, you have a complete MSX1 system with just this T7937(A) engine, and memory chips for Main RAM, Video RAM and Main ROM, making it a true 1-chip MSX.

T7937A Pinout

Name Number I/O Function
SLT3.3 60 O Slot 3-3 selection signal.
SLT2 59 O Slot 2 selection signal.
SLT1 58 O Slot 1 selection signal.
ROCE 55 O Signals access to system ROM memory. (Address between 0000h and 7FFFh of the programmed slot)
BCS 104 O Enable bidirectional data bus buffering of slots.
BRE 103 O Signals data direction to buffer control in slots.
CS1 52 O ROM page 4000h-7FFFh select signal.
CS2 53 O ROM page 8000h-BFFFh select signal.
CS12 54 O ROM pages 4000h-BFFFh select signal. (for 32kB ROM)
RFSH 132 O “Refresh” signal is active when the lower 7 bits of the address bus present the “refresh address” of the dynamic memories. At this instant, MREQ also goes to low.
WAIT 127 I This signal informs the CPU that a given memory or a certain peripheral is not yet ready for data transfer, as they are too slow.
INT 128 I This signal informs the CPU that some peripheral is requesting an interrupt. (maskable or not by program)
M1 133 O This signal indicates that the CPU is in part 1 of the machine cycle, that is, during the memory instruction fetch period.
BUSDIR 130 I This signal indicates the direction of data traffic on the data bus.
IORQ 79 O Signals the presence of an I/O address in the lower 8 bits of the address bus, thus indicating an I/O operation.
MREQ 78 O Signals the presence of complete address or refresh on the bus, indicating an operation with memory.
WR 81 O Indicates a write operation to RAM.
RD 80 O Indicates a read operation from RAM.
RSTB 61 O Indicates that the CPU has been reset, forcing the rest of the system to assume the same condition.
A0-A15 62 to 77 O System address bus.
D0, D1, D2-D7 143, 144, 1 to 6 I/O System data bus.
CLOCK 134 O CPU clock signal to synchronize external components. (f=crystal frequency /6)
RA0-RA7 43 to 50 O Switched multiplexed address bus of system dynamic-RAM memory.
SCAS 51 O Indicates the address present on the bus (RA0 to RA7) refers to the column address.
PDWR 105 O This signal enables data transfer to the printer.
PETR 126 O “Strobe” Signal for standard centronics printer.
PBSY 131 I Printer Busy
VIDEO 17 O Composite video signal.
RED 37 O Video signal “R”
GREEN 39 O Video signal “G”
BLUE 41 O Video signal “B”
Y 35 O Video signal “Y” (luminance)
MODE 16 I NTSC/PAL (H = NTSC, L = PAL)
WE 33 O Indicates video memory write operation.
RE 15 O Indicates read operation, enabling video memory output.
RB0-RB7 7 to 14 I/O Data bus for video memory.
AB0-AB7 25 to 32 O Dynamic Video RAM multiplexed address bus.
CAS 24 O Indicates that the video memory bus has column address.
RAS 23 O Indicates that the video memory bus has a line address.
CMT W 109 O Cassette output signal.
CMT ON 108 O Control signal for cassette motor on. (H = on)
CMT R 122 I Cassette input signal.
CVDD 121 Cassette internal circuit power pin. (+5V)
CGND 123 Ground pin for cassette internal circuit.
CHA 100 O PSG sound channel A output.
CHB 101 O PSG sound channel B output.
CHC 102 O PSG sound channel C output.
JA0 93 I Joystick-A up input signal.
JA1 94 I Joystick-A down input signal.
JA2 95 I Joystick-A left input signal.
JA3 96 I Joystick-A right input signal.
JABUT1 97 I/O Joystick-A trigger1 input/output signal.
JABUT2 98 I/O Joystick-A trigger2 input/output signal.
JASBCM 99 O Joystick-A com/strobe output signal.
JB0 92 I Joystick-B up input signal.
JB1 89 I Joystick-B down input signal.
JB2 88 I Joystick-B left input signal.
JB3 87 I Joystick-B right input signal.
JBBUT1 86 I/O Joystick-B trigger1 input/output signal.
JBBUT2 85 I/O Joystick-B trigger2 input/output signal.
JBSBCM 84 O Joystick-B com/strobe output signal.
PRTSEL 34 I Joystick connection form programming pin. (H = direct connection, L = external circuit connection)
K0-K7 142 to 135 I/O Set of multiplexed lines for data entry (k0 to k3) from the keyboard.
X7-X0 135 to 142 I Keyboard matrix bits.
Y0-Y8 110 to 118 I Keyboard matrix rows.
CAP 106 O Caps LED.
JIS/50 82 O JIS/50 Keyboard arrangement control.
CODE/KANA 83 O Code/Kana LED.
KS0 110 O Signal keyboard data direction for bidirectional buffer control.
KS1 111 O Enable signal for keyboard buffering.
KS2 112 O “Clock” signal for transferring scan code from keyboard rows.
KS3 113 O “Clear” signal to control the keyboard line encoding latch.
KSEL 22 I Keyboard Scan Programming. (L = direct, H = multiplexed)
CLIC 107 O Keypad trigger auditory signal output.
ICE 42 I Through this pin, you can choose to use the internal CPU in the T7937 or not. The programmed option is positive.
XT1 & XT2 21 & 20 I Points where the system clock generator crystal must be connected.
GND 56, 57, 124, 125 Ground pins.
VDD 18-19, 90-91 Power pins. (+5V)
TEST1 119 I Test pin 1. (Unused, connected to +5V)
TEST2 120 I Test pin 2. (Unused, connected to +5V)
SRSEL 36 I Programming pin to slot mapping.
SSEL1 38 I Programming pin to slot mapping
SSEL2 40 I Programming pin to slot mapping.
  • This table is the translation of the Portuguese version linked below with some fixes and additions by Acet, Pentarou and others.

T7937 revisions

There are two known revisions: the T7937 and the T7937A. The difference between them is not known.

The table below attempts to map the revisions. The table may contain errors, or it may be possible that a vendor used both revisions of the T7937 during the lifetime of the system.

Model Used chipset
Al Fateh 100 T7937A
Al Fateh 123 T7937A
Gradiente Expert DDPlus T7937A
Gradiente Expert Plus T7937A
Nikko PC-70100 T7937A
Sakhr AX-170 T7937A
Sakhr AX-230 T7937A
Toshiba HX-51 T7937
Toshiba HX-52 T7937


Links

Retrieved from "https://www.msx.org/wiki/Toshiba_T7937"